The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
In the early days of personal computing systems, peripherals were relatively simple in their functionalities. Peripherals were often coupled to the host central processing unit (CPU) via simple 2-wire serial buses, such as the Inter-Integrated Circuit (I2C) bus, or its later variant, the System Management bus (SMBUS). As peripheral functionalities increase, many peripherals began to be coupled to the host CPU using the Industry Standard Architecture (ISA) bus. Depending on the version, an ISA bus could include 62 or more pins.
In today's computing systems, notwithstanding the continuing increase in functionalities, embedded controller (EC), baseboard management controller (BMC) and super input/output (SIO) are often coupled to the host CPU through a more pin efficient Low Pin Count (LPC) bus. However, the LPC bus still requires at least 7 pins, and often, another 6 “optional” pins, a total of 13 pins. Further, on top of the still relatively high pin count, the LPC bus is still based on the old 3.3v I/O signaling technology, with the frequency of the bus clock fixed at 33 MHz. Accordingly, the LPC bus has a relatively low bandwidth of 133 Mbps. With recent advances, the LPC bus has been deemed insufficient to handle the demand of a new generation of peripheral devices, which require low cost and medium bandwidth connection.
On some platforms, peripherals may be coupled to the host CPU using the Serial Peripheral Interface (SPI) bus. The SPI bus is a 4-wire serial bus, 5-wires in some embodiments. However, the SPI bus lacks a defined protocol. At the other end, peripherals may be coupled to the host CPU through a high speed bus, such as PCI Express [PCI=Peripheral Component Interconnect]. Such solution is often considered to be too costly. Further, there exist a significant number of sideband signals used for communication between the bridging chipset and peripheral controllers, such as an EC, a BMC or a SIO, that consume significant pin cost.